NXP Semiconductors /MIMXRT1062 /ENET /EIMR

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Interpret as EIMR

TXF=TXF_0, BABR=BABR_0, TXB=TXB_0, BABT=BABT_0, GRA=GRA_0

Description

Interrupt Mask Register

Fields

TS_TIMER	TS_TIMER Interrupt Mask
TS_AVAIL	TS_AVAIL Interrupt Mask
WAKEUP	WAKEUP Interrupt Mask
PLR	PLR Interrupt Mask
UN	UN Interrupt Mask
RL	RL Interrupt Mask
LC	LC Interrupt Mask
EBERR	EBERR Interrupt Mask
MII	MII Interrupt Mask
RXB	RXB Interrupt Mask
RXF	RXF Interrupt Mask
TXB	TXB Interrupt Mask 0 (TXB_0): The corresponding interrupt source is masked. 1 (TXB_1): The corresponding interrupt source is not masked.
TXF	TXF Interrupt Mask 0 (TXF_0): The corresponding interrupt source is masked. 1 (TXF_1): The corresponding interrupt source is not masked.
GRA	GRA Interrupt Mask 0 (GRA_0): The corresponding interrupt source is masked. 1 (GRA_1): The corresponding interrupt source is not masked.
BABT	BABT Interrupt Mask 0 (BABT_0): The corresponding interrupt source is masked. 1 (BABT_1): The corresponding interrupt source is not masked.
BABR	BABR Interrupt Mask 0 (BABR_0): The corresponding interrupt source is masked. 1 (BABR_1): The corresponding interrupt source is not masked.

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